DMIPS vs MIPS: Understanding the Dhrystone Difference and Why It Matters for MCU Selection

When comparing microcontrollers, you’ll frequently see performance specifications like “120 DMIPS” or “1.25 DMIPS/MHz”. But what does DMIPS mean, and how does it differ from MIPS? More importantly, does it actually help you choose the right MCU for your project?

This article explains the difference between MIPS and DMIPS, the history of the Dhrystone benchmark, and how to correctly interpret these metrics when comparing ARM Cortex-M, RISC-V, and other processor families.

What is MIPS?

MIPS stands for Million Instructions Per Second. It’s a measure of how many machine instructions a processor can execute in one second.

The Formula:

MIPS = (Instruction Count / Execution Time) / 1,000,000

Or more practically:

MIPS = (Clock Frequency in MHz) × (Instructions Per Clock Cycle)

Example:

A processor running at 100 MHz that executes an average of 0.8 instructions per clock cycle:

MIPS = 100 MHz × 0.8 = 80 MIPS

Why MIPS Alone is Misleading

MIPS seems straightforward, but it has critical flaws:

Problem 1: Not All Instructions Are Equal

• A simple MOV (move register) takes 1 cycle
• A division might take 12 cycles
• A memory load with cache miss could take 100+ cycles

Two processors with the same MIPS rating can have vastly different real-world performance.

Problem 2: Different Instruction Sets

Consider two processors both rated at 100 MIPS:

Processor A (RISC): Takes 5 instructions to perform a task
Processor B (CISC): Takes 2 instructions to perform the same task

Even though they execute the same number of instructions per second, Processor B completes more actual work.

Problem 3: MIPS is Workload-Dependent

A processor might achieve:

• 120 MIPS running integer math
• 80 MIPS running memory-intensive code
• 60 MIPS with frequent branches

Which MIPS value is “correct”? It depends entirely on the workload.

Enter Dhrystone: A Standardized Benchmark

To make MIPS meaningful, engineers needed a standard workload that everyone could run for comparison. In 1984, Reinhold Weicker created Dhrystone.

What is Dhrystone?

Dhrystone is a synthetic benchmark program that:

• Exercises common programming operations (string manipulation, arithmetic, pointer operations, function calls)
• Contains no floating-point operations (integer-only)
• Runs for a fixed number of iterations
• Produces a score based on execution time

The output is Dhrystones per second, which can be converted to DMIPS.

What is DMIPS?

DMIPS stands for Dhrystone Million Instructions Per Second.

The Reference Point:

DMIPS is normalized against a reference system:

• VAX 11/780 minicomputer from 1977
• Running at 1 MIPS
• Producing 1757 Dhrystones/second

The Conversion:

DMIPS = (Dhrystones per second) / 1757

Example:

An ARM Cortex-M4 running at 168 MHz produces 300,000 Dhrystones/second:

DMIPS = 300,000 / 1757 = 170.7 DMIPS

DMIPS vs MIPS: Key Differences

DMIPS/MHz: Efficiency Metric

DMIPS/MHz indicates how efficiently a processor uses each clock cycle.

Formula:

DMIPS/MHz = Total DMIPS / Clock Frequency in MHz

Example Comparison:

Insight: Cortex-M7 is 71% more efficient per clock cycle than Cortex-M4, thanks to dual-issue pipeline and better branch prediction.

Real-World DMIPS Scores

ARM Cortex-M Family:

ARM Cortex-A Family:

RISC-V Examples:

How Manufacturers Report DMIPS

Example 1: STM32H743 (Cortex-M7)

Datasheet claim: “Up to 1027 DMIPS at 480 MHz”

Calculation:

DMIPS/MHz = 1027 / 480 = 2.14

This matches ARM’s specification for Cortex-M7.

Example 2: ESP32 (Xtensa LX6)

Datasheet claim: “600 DMIPS with dual-core operation at 240 MHz”

Calculation:

Total DMIPS = 600
Per core: 300 DMIPS
DMIPS/MHz per core = 300 / 240 = 1.25

Similar efficiency to Cortex-M4.

Limitations of DMIPS

1. Dhrystone is Synthetic

Dhrystone doesn’t represent real applications:

• No floating-point math
• Small code size (fits in cache)
• Predictable branches
• Minimal memory access

Your actual application will likely perform differently.

2. Compiler Optimization

Modern compilers can heavily optimize Dhrystone:

• Loop unrolling
• Function inlining
• Dead code elimination

Result: DMIPS scores can be artificially inflated with aggressive compiler flags.

3. Cache Effects

Dhrystone’s small size means it runs entirely from cache. Real applications with larger code/data will see more cache misses and slower performance.

4. No I/O or Interrupts

Dhrystone runs in isolation. It doesn’t account for:

• Interrupt latency
• DMA overhead
• Peripheral access delays
• Context switching

When DMIPS is Useful

Despite limitations, DMIPS is valuable for:

✅ Comparing Similar Architectures

Comparing STM32F4 (Cortex-M4) vs STM32F7 (Cortex-M7):

• F4: 210 DMIPS @ 168 MHz
• F7: 462 DMIPS @ 216 MHz

Conclusion: F7 is ~2x faster for computational tasks.

✅ Quick Sanity Checks

If you need “approximately 200 DMIPS of performance,” you can quickly identify:

• Cortex-M4 @ 160 MHz: ✅ (200 DMIPS)
• Cortex-M7 @ 100 MHz: ✅ (214 DMIPS)
• Cortex-M3 @ 200 MHz: ✅ (250 DMIPS)

✅ Understanding Efficiency Improvements

DMIPS/MHz shows architectural improvements:

• Cortex-M3 → Cortex-M4: Same DMIPS/MHz (1.25), added DSP instructions
• Cortex-M4 → Cortex-M7: 71% higher DMIPS/MHz (1.25 → 2.14)
• Cortex-M7 → Cortex-M55: 43% higher DMIPS/MHz (2.14 → 3.07)

When DMIPS is NOT Useful

❌ Comparing Different Workloads

DMIPS tells you nothing about:

• Floating-point performance → Use FLOPS or DSP benchmarks
• Interrupt response time → Measure with oscilloscope
• Power efficiency → Use µA/MHz or CoreMark/mW

❌ Choosing Between Architectures

Comparing Cortex-M4 (1.25 DMIPS/MHz) vs ESP32 (1.25 DMIPS/MHz) doesn’t consider:

• Integrated Wi-Fi/BLE in ESP32
• Peripheral differences
• Ecosystem maturity
• Cost

❌ Real-Time Performance

A higher DMIPS processor isn’t necessarily better for real-time:

• Cortex-M7 (2.14 DMIPS/MHz) has cache, making latency non-deterministic
• Cortex-M4 (1.25 DMIPS/MHz) has no cache, more predictable timing

Better Alternatives to DMIPS

1. CoreMark

Modern replacement for Dhrystone:

• More realistic workload
• Harder to optimize artificially
• Includes data structures, CRC, state machines

See: CoreMark Benchmark Explained

2. Application-Specific Benchmarks

Test your actual code:

void benchmark_my_app(void) {
    uint32_t start = systick_get();
    
    // Run your critical function
    process_sensor_data();
    
    uint32_t end = systick_get();
    printf("Execution time: %lu µs\n", end - start);
}

3. Real-World Profiling

Use profiling tools:

• ARM Keil µVision profiler
• Segger SystemView
• OpenOCD with GDB profiling
• Custom instrumentation with GPIO toggling

Practical Decision Framework

Step 1: Identify Your Bottleneck

• Compute-bound? (DSP, algorithms) → DMIPS matters
• I/O-bound? (sensor polling, communication) → DMIPS doesn’t matter
• Memory-bound? (large data processing) → Check bus width and memory speed

Step 2: Compare Similar Architectures

Use DMIPS to compare within the same family:

• STM32F1 vs F4 vs F7
• Nordic nRF52832 vs nRF52840
• ESP32 vs ESP32-S3

Step 3: Validate With Real Code

Once you’ve shortlisted candidates, benchmark your actual application on development boards.

Example: Choosing Between MCUs

Scenario: Motor Control Application

Requirements:

• FOC (Field-Oriented Control) algorithm
• 20 kHz control loop
• Encoder feedback processing
• CAN bus communication

Candidates:

Analysis:

DMIPS alone suggests: F746 is fastest.

But consider:

• F407 has DSP instructions (critical for FOC: multiply-accumulate, SIMD)
• F407 has hardware FPU (single-precision floating-point)
• F746 cache makes timing less predictable for 20 kHz loop

Best choice: STM32F407

• Sufficient DMIPS (210)
• DSP + FPU optimize FOC calculations
• No cache = deterministic loop timing
• Lower cost than F746

Lesson: DMIPS helped narrow choices, but architecture features mattered more.

Common Misconceptions

❌ “Higher DMIPS is always better”

Reality: More performance costs more power and money. Match performance to requirements.

❌ “DMIPS/MHz is constant across clock speeds”

Reality: Dynamic frequency scaling, memory wait states, and bus contention can change efficiency at different speeds.

❌ “Same DMIPS means same performance”

Reality: Architecture features (FPU, DSP, DMA) affect real-world performance more than DMIPS.

❌ “I can calculate DMIPS from clock speed”

Reality: You need to run Dhrystone to get accurate DMIPS. Datasheet values are measured, not calculated.

How to Run Dhrystone Yourself

On Bare Metal (ARM Cortex-M):

#include "dhrystone.h"

int main(void) {
    SystemInit();
    UART_Init();
    
    uint32_t iterations = 10000000;  // 10 million iterations
    uint32_t start = SysTick_GetTicks();
    
    Dhrystone_Run(iterations);
    
    uint32_t end = SysTick_GetTicks();
    uint32_t elapsed_ms = end - start;
    
    // Calculate Dhrystones/second
    float dhrystones_per_sec = (float)iterations / (elapsed_ms / 1000.0);
    
    // Convert to DMIPS
    float dmips = dhrystones_per_sec / 1757.0;
    
    printf("DMIPS: %.2f\n", dmips);
    printf("DMIPS/MHz: %.2f\n", dmips / (SystemCoreClock / 1000000.0));
    
    while(1);
}

Compiler Flags Matter:

# Conservative (more realistic)
arm-none-eabi-gcc -O2 dhrystone.c

# Aggressive (inflated scores)
arm-none-eabi-gcc -O3 -flto -ffast-math dhrystone.c

Always specify compiler flags when reporting DMIPS.

DMIPS in Marketing vs Engineering

Marketing Usage:

• “Up to 1027 DMIPS!” (best case, aggressive optimization)
• Used to make products sound faster
• Often lacks compiler flag details

Engineering Usage:

• “210 DMIPS @ 168 MHz with GCC -O2” (reproducible)
• Used for relative comparison
• Paired with other metrics (power, cost, peripherals)

Tip: When evaluating datasheets, look for detailed benchmark conditions. Vague DMIPS claims are less useful.

Conclusion

DMIPS vs MIPS Summary:

• MIPS = Raw instruction throughput (not standardized)
• DMIPS = Dhrystone-normalized performance (standardized, comparable)
• DMIPS/MHz = Efficiency metric (compare architectures)

When to use DMIPS:

• ✅ Comparing similar processors (STM32 F4 vs F7)
• ✅ Quick performance estimates
• ✅ Understanding architectural efficiency improvements

When NOT to rely on DMIPS:

• ❌ Choosing between different architectures without other criteria
• ❌ Real-time or deterministic performance requirements
• ❌ Floating-point or DSP-heavy workloads (use FLOPS or CoreMark)

Best practice: Use DMIPS as one data point among many: cost, power, peripherals, ecosystem, and most importantly, benchmark your actual application on candidate hardware.

Further Reading

• CPU Performance Metrics in Embedded Systems: MIPS, DMIPS, CoreMark, MHz, FLOPS
• ARM Cortex-M vs Cortex-A: Choosing the Right Architecture
• How to Choose the Right Microcontroller for Your Project
• CoreMark Official Website

Have you been confused by DMIPS specifications in MCU datasheets? Share your experience in the comments.